Instruction Pointer (IP) contains the offset from this address to next instruction byte to be fetched. Code Segment (CS) contains the base or start of current code segment. Four segment registers are used to hold upper 16 bits of starting address of four memory segments at a particular time. It contains address used to produce 20 bit address. So, the overlapping of instruction fetch with execution, called pipelining is possible. The EU simply reads instruction from queue. BIU is capable to store up to 6 bytes of instructions with FIFO manner in a queue. It has two parts: instruction queue and segment registers. It handles all transfers of data and address on the buses from EU. It sends out addresses, fetch instructions from memory, read data from memory or ports and write data to memory or ports. Internal Architecture of 8086 Microprocessor It is divided into two separate units i.e. The data bus is of 16-bit and address bus is of 20-bits. It can pre-fetch upto 6 instruction bytes from memory and queues them. Internal Architecture and Features of 8086
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